1. Field of the Invention
The present invention relates to twin MONOS memory and more particularly to twin MONOS memory either embedded in CMOS circuits or in a stand-alone application, and its fabrication method.
2. Description of the Related Art
A MONOS memory is one of typical semiconductor memories wherein carrier charge is stored in a gate insulator to have information nonvolatilely stored. The MONOS memory is of a laminated structure comprising a conductive gate (M), a top oxide film (O), a silicon nitride film (N), a tunnel oxide film (O) and a semiconductor wherein the carrier (electron or hole) is captured at a trapping level in the silicon nitride film to store the carrier charge.
A MONOS memory is disclosed as the nonvolatile memory capable of reducing the programming voltage by E. Suzuki, H. Hiraishi, K. Ishii and Y. Hayashi, “A Low-Voltage Alterable EEPROM with Metal-Oxide-nitride-Oxide and semiconductor (MONOS) Structures”, in IEEE Transaction on Electron Devices, Vol. ED-30, February 1983, p. 122). This MONOS memory is of a laminated structure comprising a conductive gate (M), a top oxide film (O), a silicon nitride film (N), a tunnel oxide film (O) and semiconductor. This structure has enabled the MONOS memory to stop hopping via the carrier trapping level in the silicon nitride film due to a potential barrier formed between the nitride film and the top oxide film, which resulted in making the nitride film as thin as possible. Further, carrier traps newly generated at the interface between the top oxide film and nitride film has enlarged a memory window to the extent it is possible to identify the stored information even if the entire insulator thickness is made thinner.
Twin MONOS individual cell structure was introduced in U.S. Pat. No. 6,255,166 to Seiki Ogura (Halo-99-001) issued on Jul. 3, 2001. Its fabrication method was presented in U.S. patent application Ser. No. 09/994,084 (Halo-01-001) to Ogura et al filed on Nov. 21, 2001. This invention also refers to an array structure of 4 bit-1 contact described in U.S. Pat. No. 6,469,935 (Halo-00-004) to Hayashi et al issued Oct. 22, 2002, where four memory storage cells share one contact. These patents are herein incorporated by reference.